FIG. 1 depicts a conventional voltage regulator 100 using an operational amplifier (op amp) and a common source transistor. The regulator comprises an op amp 110, a transistor 120, a compensation capacitor 130, and a voltage dividing feedback network 140. Transistor 120 is a PMOS transistor having a source 122, a gate 124 and a drain 126. Source 122 is connected to the voltage supply, Vcc, that is to be regulated and the regulated voltage, Vreg, is available at drain 126. Gate 124 is connected to the output of op amp 110. Power for the op amp is typically provided by the unregulated voltage supply, Vcc. The regulated voltage, Vreg, is divided by resistors 142, 144 in network 140 and the voltage at node 146 between resistors 142, 144 is applied to a non-inverting input terminal 112 of op amp 110. A reference voltage Vref is applied to an inverting input terminal 114 of the op amp 110.
In a practical application, transistor 120 is physically a relatively large device. Because of this size and the Miller effect, the gate-to-drain capacitance, Cgd, of this circuit is substantial. In addition, to ensure stability, the circuit requires compensation capacitor 130 to be connected across the gate and drain. As a result, the drain is strongly coupled to the gate and at high frequencies is coupled to the power supply, which greatly degrades the power noise rejection of the voltage regulator. In some applications, a common drain device may be used as a source follower to improve noise rejection but this results in a much reduced regulator output.
Power supply noise is often the major cause of jitter in the output clock of a phase lock loop (PLL). To minimize the PLL's sensitivity to noise, it is desirable to regulate the power supply to the analog circuit blocks of the PLL which are extremely sensitive to noise.